Floating body dynamic random access memory (DRAM) reduces the size of a DRAM memory element by eliminating a capacitor from a conventional DRAM and storing a charge in the floating body of a partially depleted SOI MOSFET. Despite a relatively small amount of charge that the floating body stores, the effect of the stored charge is magnified by altering the threshold voltage and the on-current of the partially depleted SOI MOSFET in certain operating conditions depend on the amount of charge stored in the floating body.
A basic floating body DRAM structure and its operation, as disclosed by Okhonin et al., “A Capacitor-Less 1T-DRAM Cell,” IEEE Electron Device Letters, Vol. 23, No. 2, 2002, pp. 85-87, is herein incorporated by reference. According to Okhonin et al., a compact DRAM design for a floating body DRAM results with a unit cell area of about 4 F2 through elimination of a capacitor. F is the critical dimension, or the minimum printable physical dimension, of the lithography tool used to create the physical patterns for a semiconductor structure.
Operation of an exemplary prior art floating body DRAM is described herein with accompanying figures. Referring to FIG. 1, a prior art floating body DRAM comprises a semiconductor substrate 10, a buried oxide layer 20, a top semiconductor layer 39, a gate dielectric 52, a gate conductor 54, and a spacer 52. The top semiconductor layer 39 contains shallow trench isolation (STI) regions 40, a source 70, a drain 72, a depletion zone 31, and a floating body 32. The depletion zone 31 and the floating body 32 are collectively comprise a “body”. Both the depletion zone 31 and the floating body 32 are doped substantially at the same doping level with the same type of dopants, i.e., the body (31,32) is substantially of the same doping level and of the same dopant type. Dopant concentration for the body (31,32) is within the range from 1.0×1018/cm3 to 5.0×1019/cm3, and is typically within the range from 5.0×1018/cm3 to 2.0×1019/cm3. Both the source 70 and the drain 72 are heavily doped, typically in the concentration range from 1.0×1020/cm3 to 1.0×1021/cm3, with dopants of the opposite type relative to the dopants in the body (31,32). The floating body DRAM can be implemented in an SOI PMOSFET or in an SOI NMOSFET. In the case of an SOI NMOSFET, the body 33 is doped with p-type dopants and the source 70 and the drain 72 are doped with n-type dopants. In the case of an SOI PMOSFET, the body (31,32) is doped with n-type dopants and the source 70 and the drain 72 are doped with p-type dopants. The prior art floating body DRAM in FIG. 1 is electrically isolated by the buried oxide layer 20 and by the shallow trench isolation regions 40 from adjacent devices and the substrate 10.
“Writing” of information to be stored, i.e., a “1” or a “0”, is performed by turning on the prior art floating body DRAM in FIG. 1, which is an SOI NMOSFET, by applying suitable voltage biases to the gate conductor 54, to the drain 72, and to the source 70. Depending on the combination of voltage conditions on the three terminals, i.e., on the gate conductor 54, on the drain 72, and on the source 70, either positive charges (holes) or negative charges are stored in the floating body 32. During the sensing of the stored information, either the threshold voltage or the on-current of the prior art floating body DRAM is sensed by a sense circuit.
FIGS. 2 and 3 show an implementation of a prior art floating body DRAM in an exemplary array. FIG. 2 is a vertical cross-section of the prior art floating body DRAM array along the plane of A-A′ in FIG. 3. FIG. 3 is a schematic top down view of the prior art floating body DRAM array in which only the active area, STI region, contacts, and metal level wiring are shown.
FIGS. 2 and 3 show a unit cell U of the prior art floating body DRAM array. The unit cell U is a physical implementation of a memory element that can store a single binary bit of information, The unit cell U comprises one floating body DRAM, which is a single partially doped SOI MOSFET. As can be seen in FIG. 3, a unit cell U adjoins at least another mirror image unit cell, i.e., a mirror image of the original unit cell U, along the direction of the rows within the array. A unit cell adjoins at least one other replica unit cell, i.e., an identical copy of the original unit cell, along the direction of the columns within the array. The unit cell U comprises a portion of a row of active area 33 which is isolated from neighboring rows of active area 33 by at lease one row of shallow trench isolation (STI) 42.
The prior art floating body DRAM array is formed on an SOI substrate, which comprises a semiconductor substrate 10 and a buried oxide layer 20. Each unit cell U comprises a portion of a row of active area 30, which has a source 70, a body 33, a drain 72, a portion of a gate electrode line 50, a spacer 60, a source silicide 80, a drain silicide 82, a source contact 86, a drain contact 88, a portion of a source M1 line 90, a drain M1 pad 92, a drain V1 via 98 (drawn oversized in FIG. 3 for clarity), and a portion of a drain M2 line 100. The gate electrode line 50 may comprise a gate dielectric 52 and a gate conductor line 54 as shown in FIG. 2. The gate conductor line 54 typically contains a doped gate polysilicon line 55 and a gate silicide line 56. Insulators such as rows of STI 42, a middle-of-the-line (MOL) dielectric 85, and a M1 level dielectric 95 provide electrical isolation among the electrically active components listed above. The source 70 adjoins another source 70 in a neighboring mirror image unit cell. A drain 72 adjoins another drain 72 in another neighboring mirror unit cell. The source silicide 80 adjoins a neighboring source silicide 80. A drain silicide 82 adjoins a neighboring drain silicide 82. The source contact 86 is shared with a neighboring unit cell. The drain contact 88 is also shared with a neighboring unit cell. The aspect of sharing of some of the components with neighboring unit cells is evident in the figures and thus implied in the subsequent discussions of the structures.
The unit cell U is electrically accessed by activating the source M1 line 90, the drain M2 line 100, and the gate conductor line 50 that are electrically connected to the unit cell to be accessed. The other lines may be kept deactivated, that is, not selected for a writing operation or for a sense operation. Alternatively, unit cells in one row, in one column, in a portion of a row, or in a portion of a column may be accessed at the same time by designing the architecture of the array to minimize or eliminate cross-talks, that is, interference between operations of two different unit cells. According to the architecture of the exemplary prior art floating body DRAM array in FIGS. 2 and 3, data can be stored only in the unit cells U within the same row of active area 30 at one time. Similarly, data can be read off the unit cells U within the same column, i.e., the unit cells U that are connected to the same gate conductor line 50 at one time. Alterations in the design of the architecture may allow alternate cell access schemes,
While providing advantage in the cell layout by requiring a cell area of only about 4 F2, implementation of floating body DRAM arrays faces challenges due to limitations inherent in the unit cell design. One of the key problems in the implementation of a floating body DRAM is a limited amount of charge that a floating body can store. The data is stored in the form of electrical charges in the floating body, which is sensed by the alterations in the threshold voltage of the SOI MOSFET or, more preferably, by the magnitude of the on-current of the SOI MOSFET. The larger the amount of the stored charge, the greater the change in the sense parameters, e.g., the threshold voltage or the on-current. Typical SOI MOSFET does not hold enough charges in the floating body in low voltage operations, and thus, a high voltage operation, e.g., operating voltage in excess of 2.0V in the examples in Okhonin et al., is necessary, While the capacitance of the source-body junction may be increased by increasing the doping of the body, this results in higher leakage of the SOI device.
Therefore, there exists a need for an improved floating body DRAM structure that enables a lower voltage operation by storing an increased amount of charge in the floating body.
Furthermore, there exists a need to provide a floating body DRAM structure with enhanced capacitance, and consequently, enhanced ability to store charges in the floating body without causing increases in the device leakage.